mon - fri
9am - 7pm
Design Verification Services
Analog/Mixed Signal IC Design
Digital And Analog Layout
Physical Design Engineer openings
ASIC Location: Bangalore Experience: 1 - 5 Years
Required Skills & Knowledge
BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE
Block level floor planning, power planning and IR drop analysis.
Timing closure with Xtalk and OCV
Multimode multi corner optimization and closure.
Clock tree synthesis and advanced clock tree implementation.
Blocks sizes upward of 400K Instances to 2M Instances.
Block level timing closure with sign off STA.
Block level ECO implementation involving netlist level logical changes.
Scripting experience in Perl/TCL.
Excellent debugging skills in implementation issues and ability to come up with creative solutions.
Low power technologies exposure.
Technologies from 28nm and below.
Physical Verification experience in advance nodes.
To learn more about Siliciom Technologies, please contact us at
get news and update