ul.a {list-style-type: circle;}
  • mon - fri
  • 9am - 7pm

Location: Bangalore
Experience: 1 - 5 Years
  • Qualification: B.E/M.E/M.Tech or B.S/M.S in EE/CE.
  • Responsibilities include RTL development, resolving system level challenges.
  • Architecting, implementing, documenting and validating the memory controller IP cores.
  • Candidate must have excellent Verilog and SystemVerilog concepts.
  • Experience in verification of complex RTL designs and validating them on the boards is an added advantage.
  • Working knowledge of UNIX environment and scripting languages (PERL, Python/TCL etc) desired.
  • Knowledge of AXI/AHB AMBA bus based complex multi-master & slave systems.
  • Good waveform debug skills using front end industry standard design tools like VCS, NCSIM and Questa.
  • Expertise with FPGA architecture and Xilinx implementation tools (Vivado) highly desired.
  • Excellent communication and problem solving skills.
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com

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