Solid understanding of CMOS and FinFETlayouts and process technology in 28nm and smaller.
Good understanding of basic ESD and latchup layout design considerations.
Familiarity with ASIC physical design flow:LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE.
Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc
Scripting skills for layout automation is a plus
emote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership.
Excellent written and verbal communication skills in interactions with customers, and internal development teams.
To learn more about Siliciom Technologies, please contact us at careers@siliciom.com
