Physical Design
At Siliciom, we build advanced physical design capabilities that span from block-level implementation to full-chip development, ensuring performance, reliability, and manufacturability across advanced process nodes. Our expertise covers end-to-end chip development stages including synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, IR drop/EM analysis, low-power optimization, signal integrity, and complete signoff closure using leading industry EDA platforms.
We bring strong proficiency in physical verification including DRC, LVS, antenna, and density checks across latest technology nodes such as 14nm and 10nm, combined with hands-on experience in DFT implementation (Scan, BIST, ATPG, Boundary Scan) ensuring test readiness and robust silicon yield.
Key Expertise:
- Chip Design: Fabrication, synthesis, floor planning, placement, CTS, IR drop, EM, signoff checks
- Verification: DRC, LVS, antenna, density checks (14nm, 10nm)
- DFT Techniques: Scan, BIST, ATPG, boundary scan
Flat-Level Chip Execution:
- Planning: IO, floor, power, P&R, metal fills
- Process Nodes: 14nm, 28nm+
- Flip Chip: Package-level interaction, finalization
- Partitioning & Hardening: Configuration, DFT, timing closure
Core Hardening & Optimization:
- Techniques: UPF/CPF, MMMC, timing budgeting
- Enhancements: Unique view, aging analysis
- SoC/IP Expertise: SystemVerilog
- Verification Domains: OVM/UVM/VMM, DDR, USB, Ethernet, PCIe, Video, HDMI, MIPI, DSI, CSI